`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);
assign ready_a=!valid_b|ready_b;
reg [2:0]rec_cnt;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		rec_cnt<=3'd0;
	end
	else if(valid_a&&ready_a)begin
		if(rec_cnt<3'd3)begin
			rec_cnt<=rec_cnt+3'd1;
		end
		else begin
			rec_cnt<=3'd0;
		end
	end
end
always @(posedge clk or negedge rst_n ) begin
    if(!rst_n) 
        valid_b <= 'd0;
    else if(data_cnt == 2'd3 && valid_a && ready_a)
        valid_b <= 1'd1;
    else if(valid_b && ready_b)
        valid_b <= 1'd0;
end
 
always @(posedge clk or negedge rst_n ) begin
    if(!rst_n) 
        data_out <= 'd0;
    else if(ready_b && valid_a && ready_a && (data_cnt == 2'd0))
        data_out <= data_in;
    else if(valid_a && ready_a)
        data_out <= data_out + data_in;
     
end
endmodule